The FPGA Chronicles: Ready to Probe

In the last few installments, we looked at using the Tang Nano 20K with both the GOWIN tools and some open-source tools. The open-source tools certainly had the advantage of …. The FPGA Chronicles: Ready to Probe.

The open-source tools certainly had the advantage of letting you simulate and debug your design before sending it to the actual chip. As we’ll see, the GOWIN tools include a very easy-to-use, capable logic analyzer. When you create one in the editor, you are given several complex options.

With an active GAO file, the tool builds a logic analyzer into your design, and the file sets the trigger conditions. Other times you might want an alternate configuration. If you right-click almost any file in the IDE’s Design tab, you’ll see you can disable it.

That gives it a big red X and excludes it from future builds.